DOI: 10.3724/SP.J.1089.2010.11144

Journal of Computer-Aided Design & Computer Graphics (计算机辅助设计与图形学学报) 2010/22:9 PP.1421-1427

Reducing Test Power Dissipation with Novel Power Gating Implementation

To reduce dynamic power and static power in the shift process of test procedure, a novel power gating implementation scheme is proposed. During placement phase of backend design, the registers are placed together based on the location of clock gating cells so as to physically isolate with the combinational logic. After that, power-ground network is tailored under the requirements of power gating cells. At last, the difficulties of providing separate power supply for registers and combinational logic circuits are resolved. The evaluation results on Godson-3 floating-point fused multiply-add block show that around 45% of the test power can be reduced with some penalties of area increase and no performance and test coverage degradation occurs. Moreover, it can be easily integrated into the mainstream design method.

Key words:test power,power gating,design for test,VLSI

ReleaseDate:2014-07-21 15:25:54

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