DOI: 10.3724/SP.J.1146.2012.01618

Journal of Electronics & Information Technology (电子与信息学报) 2013/35:12 PP.3011-3017

Analytical Model for Parasitic Capacitance of Tapered Through-silicon-vias with MOS Effect

An analytical model for the parasitic capacitance of tapered Through-Silicon-Vias (TSV) with MOS effect is proposed by solving Poisson’s equation. A comparison between the analytical model and Ansoft Q3D parameter extraction model is given based on copper TSV. The results show that in the bias voltage of -0.4 V, 0.5 V and 1.0 V, for the tapered TSV slop wall angles of 75°, 80°, 85° and 90°, the maximum Root Mean Square (RMS) errors of analytical model are respectively 6.12%, 4.37%, 3.34% and 4.84% over a wide range of multiple parameters; when MOS effect is ignored, the maximum RMS errors are respectively 210.42%, 214.81%, 214.52% and 211.47%, and it proves that the analytical model is accurate and the consideration of MOS effect is necessary to the analytical model. Taking into account the MOS effect, the maximum damping of S11 and the maximum increase of S21 are about 19 dB and 0.01 dB respectively, simulated by Ansoft HFSS, so the transmission performance of tapered TSV is improved.

Key words:Integrated circuit,Tapered Through-Silicon-Vias (TSV),Parasitic capacitance,MOS effect,Poisson’s equation

ReleaseDate:2014-07-21 17:04:31